1. Field of the Invention
The present invention concerns a structure of a sample-and-hold unit which can be made either in integrated circuit form on silicon or III-V group materials such as GaAs or in hybrid circuit form. The particular feature of this sample-and-hold unit is that it delivers at least twice as many samples as a standard sample-and-hold unit, even if the sampling frequency is equal to the clock frequency of the signal to be sampled.
2. Description of the Prior Art
It is known that sample-and-hold units, abbreviated as S-Hs, are used in the processing of electrical information. For example, in the digitization of an analog signal a S-H samples a number of instantaneous values of an analog signal, and these values, addressed to an analog-digital converter, are converted into a binary number.
There are different S-H structures using either a transistor or a diode bridge, but the organization common to all of them is shown schematically in FIG. 1. A switch 1 (when closed) transmits the analog signal, present at the input E to a capacitor 2. Equilibrium is set up and the capacitor 2 gets charged. The switch 1 is then opened, and the capacitor 2 transmits the memorized information, often through an amplifier, to a circuit connected to the output S which is often an analog-digital converter. Then a new sample is taken by closing the switch 1 again.
This is what is shown in FIG. 2, where a period of an analog signal 4 is sampled at the point 5. As long as the switch 1 is closed, between the points 5 and 6, the sampler follows the variation of the signal. During the time represented by the segment 6-7, the switch is open, and the capacitor 2 transmits the sample value. At 7, the switch is again closed. The sampler catches up with and then follows the signal 4 up to the next sample.
The sample-and-hold units presently available in the market have acquisition times (&lt;500 ps) that make it possible to obtain input signal frequencies of up to 1 GHz. This acquisition time depends on the memorizing capacity.
Thus, in a sample-and-hold unit, the output signal is broken down into a sequence of stages of catching up with, following and holding the input signal. Of all these stages, the only really interesting ones are the holding stages which correspond to the information contained earlier in the input signal. The other stages, although inherent to the system, contain no useful information. For it to be possible to reconstitute the input signal, the frequency of the sampling signal should be at least twice that of the input signal. This therefore calls for two samples to be taken during one period of the input signal in order to comply with the Nyquist theorem or Shannon theorem. In FIG. 2, the signal 4 should be sampled, for example, at 5 or 8, during one period.
At microwave frequencies, increasing the sampling frequency becomes complicated owing to the uncertainty about the instant of opening or closing of the switch 1, which remains a semiconductor device having, therefore, a switching time.
The architecture of the S-H according to the present invention enables doubling of at least the number of samples given during a period of the input signal, without modifying the sampling frequency or, in what amounts to the same thing, doubling the frequency of the input signal without adversely affecting the linearity performance characteristics.
This result is obtained by means of an S-H structure in which at least two sampling channels work in parallel. These channels are controlled either by the two complementary signals H and H of one and the same clock, if there are only two channels or by the phase-shifted signals of one and the same clock if there are more than two channels. But irrespectively of the number of channels in parallel, only the holding stages are transmitted at the output. Consequently, a first channel may follow the signal while a second channel transmits it at the output and a third channel catches up with the signal.